1. Field
The present invention relates to the field of semiconductor manufacturing, specifically a planar Tunneling Field Effect Transistor (TFET) which features asymmetric source/drain terminals and a silicon germanium alloy epitaxial source region.
2. Description of Related Art
As MOSFET gate length scaling continues, controlling short channel effects such as drain induced barrier lowering and sub-threshold swing is imperative for improved performance. Tunnel Field Effect Transistors (TFET's) can improve both of these parameters by changing the injection mechanism and provide asymmetric doping to the source and drain regions of the device. Asymmetric processing has limited the prior TFET fabrication attempts to vertical growth of the source, channel, and drain regions, requiring a side gate oxide and gate electrode deposition. This process suffers from high overlap capacitance between the gate and source/drain regions which adversely increases the transistor gate delay and limits the device to a single channel length. The TFET also suffers from high gate leakage due to the oppositely biased source and gate nodes.
In a conventional MOSFET, sub-threshold swing is limited by the diffusion of carriers over the source to channel barrier where the injection current is proportional to kT/q; hence at room temperature, 25 C, sub-threshold swing is 60 mV/dec. In a TFET, injection is governed by band to band tunneling from the valence band of the source to the conduction band of the channel which can achieve much lower sub-threshold swing. DIBL and off-state leakage, other short channel affects, are limited by the n vs. p doping asymmetry of the source to drain.